In many non-volatile computer memories, the ability to store data is often related to the amount of current that flows through a particular storage unit during the programming process. One particular example of a non-volatile memory is a Flash or EEPROM memory where the state of a storage unit within the memory is dependent on the amount of charge stored on a floating gate. In general terms, the greater the current that flows through a given unit, the quicker it can be programmed, the wider range of levels to which it can be programmed, or both. However, as a large number of storage units are generally programmed in parallel, with the trend being towards even greater numbers, this results in high current levels, both on average and instantaneously, that are at odds with the trend to lower power devices.
Non-volatile data storage devices, such as electronically erasable programmable read-only memories (EEPROM) or flash memories, are widely used in portable devices lacking a mass data storage devices and a fixed source of power, such as cellular phones, handheld personal computers (PCs), portable music players and digital cameras.
Flash memories are typically semiconductor field effect transistor devices having a number of storage elements each one or more isolated floating gates programmed to store information by injecting charge on the floating gate to change a threshold voltage of the transistor. The injected charge changes the threshold voltage from an intrinsic threshold voltage by an amount proportional to the amount of stored charge. The new threshold voltage of the transistor represents one or more bits of programmed data or information. For example, in a simple memory cell storing a single bit of data, the threshold voltage of the transistor is either raised to a value near a high end of the threshold voltage space or maintained at a value near a low end. These two programmed threshold voltages represent a logical one or a logical zero, and program the memory cell to either turn on or not, respectively, when read conditions are established, thereby enabling a read operation to determine if data stored in the memory cell is a logical one or a logical zero.
Non-volatile memories in general, and Flash EEPROM devices in particular, are discussed more fully in a number of patents and patent applications for various architectures and cell structures. A NOR array of one design has its memory cells connected between adjacent bit (column) lines and control gates connected to word (row) lines. The individual cells contain either one floating gate transistor, with or without a select transistor formed in series with it, or two floating gate transistors separated by a single select transistor. Examples of such arrays and their use in storage systems are given in the following U.S. patents and pending applications of SanDisk Corporation that are incorporated herein in their entirety by this reference: U.S. Pat. Nos. 5,095,344, 5,172,338, 5,602,987, 5,663,901, 5,430,859, 5,657,332, 5,712,180, 5,890,192, and 6,151,248, and Ser. Nos. 09/505,555, filed Feb. 17, 2000, and 09/667,344, filed Sep. 22, 2000.
A NAND array of one design has a number of memory cells, such as 8, 16 or even 32, connected in series string between a bit line and a reference potential through select transistors at either end. Word lines are connected with control gates of cells in different series strings. Relevant examples of such arrays and their operation are given in the following U.S. patent application Ser. No. 09/893,277, filed Jun. 27, 2001, that is also hereby incorporated by reference, and references contained therein.
EEPROM programming mechanisms include drain side Channel Hot Electron Injection, in which a high voltage on the control gate and another high voltage on the drain cause hot electrons to cross from the drain side of the channel to the floating gate through a thin oxide layer, and Source Side Injection. For Source Side Injection, the presence of a select gate or side-wall can be used to create a select transistor in series with the floating gate transistor. In Source Side Injection a voltage, slightly greater than the threshold voltage of the select transistor is placed on the select gate, a high voltage is capacitively coupled to the floating gate by applying a high voltage to the control gate, and a high voltage is applied to the drain of the floating gate transistor. The voltage on the select gate is sufficient to turn on a portion of the channel under the select gate. The differential voltage between the source and drain generates channel hot electrons at the gap between the select gate and the floating gate which are then swept to the floating gate by a favorable electric field in the gap oxide near the source side of the floating gate.
The latest generation of flash memories can have arrays of hundreds of millions of memory cells which are programmed and erased in sectors or programming blocks ranging in size from 128 to 64K bytes, where the erase and the programming blocks are often not the same size. The programming of large numbers of memory cells is described, for example, in a U.S. patent application entitled “Pipelined Parallel Programming Operation in a Non-Volatile Memory System” by Kevin M. Conley and Yoram Cedar, filed Feb. 22, 2002, that is also hereby incorporated by reference, and references contained therein. Power consumed in programming the large number of memory cells in a sector has become a significant problem in conventional flash memories. It is particularly a problem for portable devices that rely on batteries and generally have an on-chip voltage supply or charge pump with a limited power capacity. Moreover, the trend in many portable devices, such as cellular phones and digital cameras, has been towards smaller devices or form factors. Thus, the increasing number memory cells and the shrinking battery sizes in portable devices have introduced further limitations on the ability to program large numbers memory cells in parallel.
Another concern in flash and other non-volatile memories is performance, particularly the speed of programming in multi-state memories. The dominant multi-level data conditional programming methodology currently in use for fast, high precision programming of non-volatile memories is the controlled bias (e.g. via staircase voltage pulse train) steering (or control) electrode implementation. It has been the approach of choice because it enables spanning the full range of voltage conditions required to program to the corresponding range of target states (as well as accommodate the cell to cell variations in programming characteristics) to effect precise programming in a minimum amount of time. In the majority of hot-electron programming based FLASH and EEPROM cells, this approach is effective because it is able to handle the highly non-linear program rate with applied steering voltage, wherein programming speed increases exponentially with voltage (an essential feature in order to, at the same time, meet the long term retention requirements under the lower voltage read/storage conditions). Furthermore, the use of fixed voltage and varying time is generally considered unattractive-if voltage is too low for the target state, programming becomes unacceptably slow, whereas if too high, programming speed becomes too fast to adequately control the programmed level with the precision required for multi-level storage.
One preferred embodiment of this write data conditional steering methodology is to provide individual steering conditions to each of the group of cells being programmed at a given time, dependent on target state. This requires a cell/array that supports “column-oriented” steering, allowing the data-dependent cell programming condition/stimulus to be applied, not only to the bit line (which primarily acts as a on/off switch to enable or disable any programming in this arrangement), but also to the cells' steering gates, on a cell-by-cell basis. Such an approach is described in U.S. Pat. No. 6,317,363, which is hereby incorporated by reference. This further improves multi-level write performance by allowing optimized conditions for each state to be used, rather than forcing a common set of conditions to all the cells (i.e. independent of individual cell target data), for cells/arrays in which all steering gates in the unit cell block being written are tied together.
The price of this column-oriented steering is the increased overhead (die area and circuit complexity) required to provide the individual steering condition needs to the thousands of cells being simultaneously programmed. Without data-dependent storage element conditions, multi-state programming is slower than binary programming. Additionally, some embodiments of data-dependent programming may not be economical, or may necessitate using larger than optimal erase blocks in order to better amortize the extra area required for circuits that implement the data-dependent programming over a larger erase blocks. Given the increased importance of both operating speed and storage capacity, there is an increasing need for data dependent programming of multi-state non-volatile memories, but preferably without the overhead area and complexity of the added column-oriented steering implementation.
The present invention provides a solution to these and other problems, and offers other advantages over the prior art.